Semiconductor memory devices are used to store digital data. These memory devices are typically used in computer processing systems where a processor can read data from and write data to the memory device. There are various types of memory devices, including volatile memory and non-volatile memory. Generally, volatile memory devices will store data only when power is applied. In contrast, non-volatile memory can continue to store data even when power is no longer applied. A common volatile memory is synchronous dynamic random access memory (“SDRAM”).
The SDRAMs are “synchronous” because a clock signal is applied to the memory device, and operation of the SDRAM is based on the clock signal. For example, a read command is provided to the SDRAM by a processor in the form of a combination of command signals. The logic states of the command signals are latched in response to a rising edge of the clock signal. A command decoder decodes the latched read command and generates internal signals to perform the read operation. At a known time after the read command is latched, data is provided at input-output data terminals to be read. The time is typically specified in terms of the number of clock cycles that elapse after the read command is latched. By having the SDRAM and the processor synchronized to the same clock signal, the processor will be able to latch the data at a known time after it issued the read command. Having synchronous operation also allows commands to be provided to the SDRAM in a “pipeline” fashion, where the commands are issued one after another in response to the clock signal, rather than waiting until a previous operation completes before issuing a new command.
The SDRAM devices are designed to be used in a variety of applications and conditions, such as different voltage conditions, different timing conditions, different power conditions, and the like. As a result, SDRAM devices are designed with various programmable operating modes that can be set to enable operation in the various conditions or environments. Examples of programmable operating modes includes burst length, CAS latency, test mode option, and the like. The operating modes are typically programmed through the use of mode registers, which can be programmed with binary digits, or bits, that correspond to the desired option of each of the operating modes defined for the register. The bits of a mode register are allocated to the operating modes defined for the register in a way to provide a suitable number of options for the particular operating mode. For example, if it is desirable for an operating mode, such as CAS latency, to have four different choices, then two bits are defined for selecting one of four CAS latency options. In contrast, for an operating mode, such as a test mode option where the options are either normal operation or test mode operation, only one bit needs to be defined for selecting the desired operating mode for the test mode option. Additionally, all of the bits of a mode register are typically allocated to the operating modes defined for the mode register. That is, if a mode register is 12-bits wide, and has six operating modes defined, changing the bit allocation or the operating modes defined for the mode register requires one of the six operating modes to sacrifice a bit allocated to it or eliminating one of six the operating modes from the mode register.
Neither approach is desirable because changing the operating mode definitions for a mode register or the bit allocation for the operating modes may preclude use of the memory device in legacy systems. That is, the operating modes of a new memory device may not be programmed correctly by a memory controller of an older legacy system that is compatible with an older memory device. In designing a memory device, however, to the extent possible, it is desirable for the memory device to be designed to have the flexibility to work in newer applications as well as work in legacy systems. For example, newer applications often have system clocks having much higher frequency than legacy systems. In some cases, the clock frequency can be two- or three-times the frequency of an older system. It is desirable for a memory device to be able to function in both environments. However, it may be difficult to provide a sufficient number of options for an operating mode that works with both a legacy system and the new application.
One such operating mode is CAS latency, which is a delay in clock cycles between the registration of a read command by the memory device and the availability of the first bit of output data on the data terminals. A CAS latency is needed since a minimum time is required for the memory device to complete a read operation internally. With the internal access time essentially fixed, the number of clock cycles defining the delay is different for different clock frequencies. Generally, the appropriate CAS latency for higher frequency clocks is greater than for lower frequency clocks. Thus, in order for a memory device to have applicability for different systems having different system clock frequencies, the memory device should have a sufficiently broad range of CAS latencies.
Even if the memory device is designed to have a greater range of CAS latencies by increasing the number of bits allocated to selecting a CAS latency, however, the modification of the mode register to accommodate the greater number of selections may result in another problem that also limits the applicability of the memory device in legacy systems. Namely, by changing the bit definition of the CAS latency operating mode, for example, by increasing the bits used to select a CAS latency, the memory controller of a legacy system may be unable to program the appropriate CAS latency under the new definition for the CAS latency operating mode. That is, the memory controller of the legacy system may be incapable of programming the additional bit now allocated to selecting a CAS latency since at the time the memory controller was programmed, the definition of options for the CAS latency operating mode was different. Additionally, as previously discussed, allocating another bit to the CAS latency operating mode will most likely require redefining the bit allocation for the other operating modes, or moving an operating mode to another mode register. In this case, the memory controller in a legacy system that was programmed to set the various operating modes for a memory device will be completely unsuitable for programming a newer memory device having operating mode definitions completely different than the definitions for which the memory controller was programmed to select.
Therefore, there is a need for an alternative apparatus and methods that can be used to provide additional selectable options for an operating mode, and in some applications, allow for compatibility with legacy systems.